[询问]CPLD 和 FPGA

CCYAP

谁知道CPLD 和 FPGA 的分别是什么吗？

jamyang

CPLD- complex programmable logic device. ...
FPGA - Field programmable gates array

kind of microprocessor but both of the architecture are different and CPLD is more advance
u can get some info from these devices manufacturer ..
www.xilinx.com

pic

请问CPLD 和 FPGA的价钱会昂贵吗？最便宜的多少钱？
还有，容易购买吗？

CCYAP

CPLD 通常用在哪里？FPGA呢？FPGA和CPLD能共用吗？

jchin2000

FPGA 可以用来做FFT, IFFT, FIR 等等。
有谁有更多资料，我也要了解多一点关于FPGA。

EvoN160

CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with complexity between that of FPGAs and PALs, and architectural features from both. The building block of a CPLD is the macro cell, which contains logic implementing sum-of-products expressions and more specialized logic operations.

Features in common with PALs:

Non-volatile configuration memory. Unlike an FPGA, an external configuration PROM isn't required, and the CPLD can function immediately on system start-up.
For all but the largest devices, routing constrains most logic blocks to have input and output signals connected to external pins (little opportunity for internal state storage or deeply layered logic).
Features in common with FPGAs:

Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions (such as integer arithmetic).
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. The differences in architectural approach become more apparent farther from this intermediate region.

This characteristic of non-volatility means that CPLDs are often used in modern digital design to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.


也就是说, CPLD 及 FPGA 是有引用在不同的地方. 比方说, 我们电脑主机板上的CMOS就可用CPLD来设计, 因为它有类似ROM的特性. 而我们的CPU就可以用FPGA来设计...

至于价格方面, 简单的开发board大概少过RM1000. 如果要,可以email我. [email protected]